In semiconductor devices, contacts (e.g., substrate contacts, low resistance contacts, contacts to an N+ buried plate, etc.) are frequently included in device design to perform various functions and features of/in the finished device. Formation of these contacts frequently requires inclusion of a number of steps in the semiconductor manufacturing/fabrication process. These steps include etching portions of the semiconductor device to go through formed layers and expose the substrate and/or using a device contact level silicide and/or a (MOL) metal to connect to the N+ buried plate. These processes require a hole to be formed/etched through layers of the semiconductor device and the contact to be positioned within the hole formed in the existing structure. However, in some semiconductor devices (e.g., newer designs, new technologies, smaller design and/or build devices, etc.), etching these holes/contacts and creating a low resistance contact may be problematic due to process integration adjustments and requirements. Further, this etching and formation may create structures on the wafers which are problematic for an integrated process flow (e.g., a non-planar contact structure, deep hole on the wafer, etc.).